In today'information age, networking and communications applications are increasingly hungry for information bandwidth. With increased demand for bandwidth comes ever increasing requirements on Quality of Service (QoS) to better guarantee the integrity of data and to maximize system up-time. For this purpose, intelligent routing management is often employed. For example, in packet distribution routing, data streams are reorganized into small packets of data, each of which is routed through separate data paths en route to the final destination, where the packets are ultimately reconstructed into the original data streams. Such routing can only be achieved via complex deep packet processing, which requires ever faster and more powerful NPUs & ASICs.
The increased demands on data processing have, not surprisingly, impacted the design of internal hardware design, especially in the area of on-board power distribution. Since the standard size of a communications board remains relatively constant, power distribution systems must be implemented in an ever decreasing space, as future designs require more and more processors to be added to the board. At the same time, the increase in component count invariably increases power consumption. To fit a power supply into a smaller space and to satisfy the increased demands for power, power distribution design should be optimized to ensure efficiency. Designing more efficient power supplies creates less dissipation and therefore less heat.
Many of today'networking and communications systems employ a power architecture that receives a 48V nominal input from a bulk AC/DC rectifier module. The 48V input is a nominal input, but various systems will accept a power input within a range on either side of nominal. For instance, the universal telecom voltage range is from 36Vin to 75Vin, and the ETSI (European Telecom Standard Input) voltage range is from 36V to 60V. Other systems operate from a regulated 48V bus +/−10%. Regardless of which power distribution method is employed, the input voltage should be distributed to the point-of-load in the most electrically efficient and cost effective way possible.
To meet these more demanding requirements, two-stage power conversion is becoming the new standard for on-board power delivery. Traditionally, multiple isolated power converters 105a, . . . , 105n−1, 105n called “bricks” were used to power various low voltage loads on a board, such as a computer motherboard, as shown in FIG. 1. Lower current peripheral outputs were supplied by converting the intermediate power produced by one of these “bricks” via POLs 110a . . . 110n. 
Then, in an effort to increase the simplicity and flexibility of on-board power distribution design, fully regulated converter were used to generate intermediate bus voltages, which were then convened to point-of-load voltages via point-of-load power converters (POLs). For example, in one scheme (not shown), a −48Vin nominal input is converted into a 3.3 volt intermediate bus voltage using a single isolated converter. This intermediate bus voltage is supplied directly to the most power-hungry loads on the board, while less power-hungry loads receive power via respective POL converters. In order to maximize throughput efficiency and minimize cost of either two-stage scheme, each power conversion stage must be carefully optimized. However, throughput efficiency of these schemes is typically low.